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CXD3412GA
Timing Generator and Signal Processor for Frame Readout CCD Image Sensor
Description The CXD3412GA is a timing generator and CCD signal processor IC for the ICX412 CCD image sensor. Features * Timing generator functions * Horizontal drive frequency 22.5MHz (base oscillation frequency 45MHz) * Supports frame readout/draft (sextuple speed)/ AF (auto focus) * High-speed/low-speed shutter function * Horizontal and vertical drivers for CCD image sensor * CCD signal processor functions * Correlated double sampling * Programmable gain amplifier (PGA) allows gain adjustment over a wide range (-6 to +42dB) * 10-bit A/D converter * Chip Scale Package (CSP): CSP allows vast reduction in the CCD camera block footprint Applications Digital still cameras Structure Silicon gate CMOS IC Applicable CCD Image Sensors ICX412 (Type 1/1.8, 3240K pixels) 96 pin LFLGA (Plastic)
Absolute Maximum Ratings * Supply voltage VDDa, VDDb, VDDc, VDDd VSS - 0.3 to +7.0 V VDDe, VDDf, VDDg VSS - 0.3 to +4.0 V VL -10.0 to VSS V VH VL - 0.3 to +26.0 V * Input voltage (analog) VIN VSS - 0.3 to VDD + 0.3 V * Input voltage (digital) VI VSS - 0.3 to VDD + 0.3 V * Output voltage VO1 VSS - 0.3 to VDD + 0.3 V VO2 VL - 0.3 to VSS + 0.3 V VO3 VL - 0.3 to VH + 0.3 V * Operating temperature Topr -20 to +75 C * Storage temperature Tstg -55 to +125 C Recommended Operating Conditions * Supply voltage VDDd 3.0 to 5.5 VDDa, VDDb, VDDc, VDDd, VDDe, VDDf, VDDg 3.0 to 3.6 VM 0.0 VH 14.5 to 15.5 VL -7.0 to -8.0 * Operating temperature Topr -20 to +75
V V V V V C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E02217-PS
CXD3412GA
Block Diagram
TEST3 TEST4 TEST5 DVDD1 DVDD2 AVDD3 AVDD4 DVSS3 DVSS1 DVSS2
AVSS3
AVSS4
AVSS5
SCK2
A1 A2 C7 D8 D7
B8 B6 B9 A6 C5
A3 A4 B4
SEN2
SSI2
NC
NC
C3
C2
C1
A5 C4
B5
E2 F2 F3
E3 F1
C4 C8 AVDD5 A9 AVSS6 A8 C7 B7 C8 A7 C9 C6 CCDIN C9 AVDD1 E9 AVDD2 E8 AVSS1 D9 AVSS2 E7 XSHPI F9 XSHDI F8 PBLKI F7 XSHP G9 XSHD G8 PBLK G7 XRS H7 VDD4 H8 VDD2 K7 RG K8 VSS2 K9 VDD3 H9 H1 J8 H2 J9 VSS3 J7 ID/EXP N9 WEN M9 L2 VH M5 VM L4 VL M6 Serial Port Register V Driver SSI1 M1 SCK1 N1 SEN1 SSG L8 SSGSL Latch 1/2 Selector Pulse Generator CDS PGA ADC Latch DAC Serial Port Register B3 B2 B1 D0 (LSB) D1 D2
C3 D3 C2 D4 C1 D5 D3 D6 D2 D7 D1 D8 E1 Preblanking Dummy Pixel Auto Zero Black Level Auto Zero D9 (MSB) ADCLKI CLPOBI CLPDMI VSS4 ADCLK CLPOB CLPDM VSS5 OSCI OSCO CKI CKO MCKO
G1 G2 G3 L3 H1 H2 H3 J3 L1 K1 J1 J2 K2
N8 SNCSL
M8 M3 M7
L5 N5 M4 L6
N6 N4 N7
N2 M2
Selector
L9
K3 L7
N3
VSS1
VDD1
TEST1
TEST2
-2-
VDD5
VSS6
RST
V1A
V1B
V3A
V3B
SUB
HD
VD
V2
V4
CXD3412GA
Pin Configuration (Top View)
A B C D E F G H J K L M N
NC D2 D5 D8 D9 DVSS2 ADCLKI ADCLK CKI OSCO OSCI SCK1 SEN1 1
NC D1 D4 D7 DVDD1 DVSS3 CLPOBI CLPOB CKO MCKO SSI1 VD HD 2
SCK2 D0 D3 D6 DVSS1 DVDD2 CLPDMI CLPDM VSS5 VDD5 VSS4 TEST1 VSS6 3
SSI2 SEN2 TEST4
TEST3 TEST5 AVSS5
AVSS4 AVDD4 C9
C8 C7 C3 C1 AVSS2 PBLKI PBLK XRS VSS3 VDD2
AVSS6 AVDD3 C4 C2 AVDD2 XSHDI XSHD VDD4 H1 RG SSGSL RST SNCSL 8
AVDD5 AVSS3 CCDIN AVSS1 AVDD1 XSHPI XSHP VDD3 H2 VSS2 VDD1 WEN ID/EXP 9
VM V2 V4 4
V1A VH V1B 5
V3A VL V3B 6
VSS1 TEST2 SUB 7
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CXD3412GA
Pin Description Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 C1 C2 C3 C4 C5 C6 C7 C8 C9 D1 D2 D3 D7 D8 D9 E1 E2 E3 E7 Symbol NC NC SCK2 SSI2 TEST3 AVSS4 C8 AVSS6 AVDD5 D2 D1 D0 SEN2 TEST5 AVDD4 C7 AVDD3 AVSS3 D5 D4 D3 TEST4 AVSS5 C9 C3 C4 CCDIN D8 D7 D6 C1 C2 AVSS1 D9 DVDD1 DVSS1 AVSS2 I/O -- -- I I I -- -- -- -- O O O I I -- -- -- -- O O O I -- -- -- -- I O O O -- -- -- O -- -- -- No connected. (Open) No connected. (Open) CCD signal processor block serial interface clock input. (Schmitt trigger) CCD signal processor block serial interface data input. (Schmitt trigger) CCD signal processor block test input 3. Connect to DVSS. CCD signal processor block analog GND. Capacitor connection. CCD signal processor block analog GND. CCD signal processor block analog power supply. ADC output. ADC output. ADC output (LSB). CCD signal processor block serial interface enable input. (Schmitt trigger) CCD signal processor block test input 5. Connect to DVDD. CCD signal processor block analog power supply. Capacitor connection. CCD signal processor block analog power supply. CCD signal processor block analog GND. ADC output. ADC output. ADC output. CCD signal processor block test input 4. Connect to DVSS. CCD signal processor block analog GND. Capacitor connection. Capacitor connection. Capacitor connection. CCD output signal input. ADC output. ADC output. ADC output. Capacitor connection. Capacitor connection. CCD signal processor block analog GND. ADC output (MSB). CCD signal processor block digital power supply. (Power supply for ADC) CCD signal processor block digital GND. (GND for ADC) CCD signal processor block analog GND. -4- Description
CXD3412GA
Pin No. E8 E9 F1 F2 F3 F7 F8 F9 G1 G2 G3 G7 G8 G9 H1 H2 H3 H7 H8 H9 J1 J2 J3 J7 J8 J9 K1 K2 K3 K7 K8 K9 L1 L2
Symbol AVDD2 AVDD1 DVSS2 DVSS3 DVDD2 PBLKI XSHDI XSHPI ADCLKI CLPOBI CLPDMI PBLK XSHD XSHP ADCLK CLPOB CLPDM XRS VDD4 VDD3 CKI CKO VSS5 VSS3 H1 H2 OSCO MCKO VDD5 VDD2 RG VSS2 OSCI SSI1
I/O -- -- -- -- -- I I I I I I O O O O O O O -- -- I O -- -- O O O O -- -- O -- I I
Description CCD signal processor block analog power supply. CCD signal processor block analog power supply. CCD signal processor block digital GND. CCD signal processor block digital GND. CCD signal processor block digital power supply. Pulse input for horizontal and vertical blanking period pulse cleaning. (Schmitt trigger) CCD data level sample-and-hold pulse input. (Schmitt trigger) CCD precharge level sample-and-hold pulse input. (Schmitt trigger) Clock input for analog/digital conversion. (Schmitt trigger) CCD optical black signal clamp pulse input. (Schmitt trigger) CCD dummy signal clamp pulse input. (Schmitt trigger) Pulse output for horizontal and vertical blanking period pulse cleaning. CCD data level sample-and-hold pulse output. CCD precharge level sample-and-hold pulse output. Clock output for analog/digital conversion. Logical phase can be adjusted by serial interface data. CCD optical black signal clamp pulse output. Horizontal/vertical OB pattern can be changed by serial interface data. CCD dummy signal clamp pulse output. Sample-and-hold pulse output for analog/digital conversion phase alignment. Timing generator block digital power supply. (Power supply for CDS block) Timing generator block 3.0 to 5.0V power supply. (Power supply for H1/H2) Inverter input. Inverter output. Timing generator block digital GND. Timing generator block digital GND. CCD horizontal register clock output. CCD horizontal register clock output. Inverter output for oscillation. When not used, leave open or connect a capacitor. System clock output for signal processor IC. Timing generator block digital power supply. (Power supply for common logic block) Timing generator block digital power supply. (Power supply for RG) CCD reset gate pulse output. Timing generator block digital GND. Inverter input for oscillation. When not used, fix to low. Timing generator block serial interface data input. Schmitt trigger input.
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CXD3412GA
Pin No. L3 L4 L5 L6 L7 L8 L9 M1 M2 M3 M4 M5 M6 M7
Symbol VSS4 VM V1A V3A VSS1 SSGSL VDD1 SCK1 VD TEST1 V2 VH VL TEST2
I/O -- -- O O -- I -- I I/O I O -- -- I
Description Timing generator block digital GND. Timing generator block digital GND. (GND for vertical driver) CCD vertical register clock output. CCD vertical register clock output. Timing generator block digital GND. Internal SSG enable. High: Internal SSG valid, Low: External sync valid Timing generator block serial interface clock input. Schmitt trigger input. Vertical sync signal input/output. Timing generator block test input 1. Normally fix to GND. CCD vertical register clock output. Timing generator block 15.0V power supply. (Power supply for vertical driver) Timing generator block -7.5V power supply. (Power supply for vertical driver) Timing generator block test input 2. Normally fix to GND. (With pull-down resistor) (With pull-down resistor) (With pull-down resistor)
Timing generator block digital power supply. (Power supply for common logic block)
M8 M9 N1 N2 N3 N4 N5 N6 N7 N8 N9
RST WEN SEN1 HD VSS6 V4 V1B V3B SUB SNCSL ID/EXP
I O I I/O -- O O O O I O
Timing generator block reset input. High: Normal operation, Low: Reset control Normally apply reset during power-on. Schmitt trigger input/No protective diode on power supply side. Memory write timing pulse output. Timing generator block serial interface strobe input. Schmitt trigger input. Horizontal sync signal input/output. Timing generator block digital GND. CCD vertical register clock output. CCD vertical register clock output. CCD vertical register clock output. CCD electronic shutter pulse output. Control input used to switch sync system. High: CKI sync, Low: MCKO sync (With pull-down resistor)
Vertical direction line identification pulse output/exposure time identification pulse output. Switching possible using the serial interface data. (Default: ID)
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CXD3412GA
Electrical Characteristics Timing Generator Block Electrical Characteristics DC Characteristics Item Supply voltage 1 Supply voltage 2 Supply voltage 3 Supply voltage 4 Input voltage 11 Input voltage 22 Pins VDD2 VDD3 VDD4 VDD1, VDD5 RST, SSI1, SCK1, SEN1 Symbol VDDa VDDb VDDc VDDd VI+ VI- 0.7VDDd 0.3VDDd 0.8VDDd 0.2VDDd Feed current where IOH = -1.2mA Pull-in current where IOL = 2.4mA Feed current where IOH = -22.0mA VDDb - 0.8 Pull-in current where IOL = 14.4mA Feed current where IOH = -3.3mA Pull-in current where IOL = 2.4mA Feed current where IOH = -3.3mA Pull-in current where IOL = 2.4mA Feed current where IOH = -6.9mA Pull-in current where IOL = 4.8mA Feed current where IOH = -3.3mA Pull-in current where IOL = 2.4mA Feed current where IOH = -2.4mA Pull-in current where IOL = 4.8mA V1A/B, V2, V3A/B, V4 = -8.25V V1A/B, V2, V3A/B, V4 = -0.25V V1A/B, V3A/B = 0.25V V1A/B, V3A/B = 14.75V SUB = -8.25V SUB = 14.75V 5.4 -4.0 5.0 -7.2 10.0 -5.0 VDDd - 0.8 0.4 VDDd - 0.8 0.4 VDDd - 0.8 0.4 VDDc - 0.8 0.4 VDDa - 0.8 0.4 0.4 VDDd - 0.8 0.4 (Within the recommended operating conditions) Conditions Min. 3.0 3.0 3.0 3.0 0.8VDDd 0.2VDDd Typ. 3.3 3.3 3.3 3.3 Max. 3.6 5.25 3.6 3.6 Unit V V V V V V V V V V V V V V V V V V V V V V V V mA mA mA mA mA mA
TEST1, TEST2, VIH1 SNCSL, SSGSL VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3
Input/output voltage
VD, HD
Output voltage 1 Output voltage 2 Output voltage 3 Output voltage 4 Output voltage 5 Output voltage 6
H1, H2 RG
XSHP XSHD, , XRS, PBLK, VOH4 CLPOB, CLPDM, VOL4 ADCLK CKO MCKO ID/EXP , WEN V1A, V1B, V3A, V3B, V2, V4 VOH5 VOL5 VOH6 VOL6 VOH7 VOL7 IOL IOM1 IOM2 IOH IOSL SUB IOSH
Output current 1
Output current 2
1 This input pin is a schmitt trigger input and it has protective diode of the power supply side in the IC. It is not supported to 5V input. 2 These input pins are with pull-down resistor in the IC. Note) This table indicates the conditions for 3.3V drive. -7-
CXD3412GA
Inverter I/O Characteristics for Oscillation Item Logical Vth Input voltage Output voltage Feedback resistor Oscillation frequency Pins OSCI OSCI OSCO OSCI, OSCO OSCI, OSCO Symbol LVth VIH VIL VOH VOL RFB f Conditions
(Within the recommended operating conditions) Min. 0.7VDDd 0.3VDDd Typ. VDDd/2 Max. Unit V V V V 0.4 500k 20 2M 5M 50 V MHz
Feed current where IOH = -3.6mA Pull-in current where IOL = 2.4mA VIN = VDDd or VSS
VDDd - 0.8
Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment (Within the recommended operating conditions) Item Logical Vth Input voltage Input amplitude CKI Pins Symbol LVth VIH VIL VIN fmax 50MHz sine wave 0.3 0.7VDDd 0.3VDDd Conditions Min. Typ. VDDd/2 Max. Unit V V V Vp-p
Note) Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude is the input amplitude characteristics in the case of input through a capacitor. Switching Characteristics Item Rise time Symbol TTLM TTMH TTLH TTML Fall time TTHM TTHL VCLH Output noise voltage VCLL VCMH VCML VL to VM VM to VH VL to VH VM to VL VH to VM VH to VL Conditions (VH = 15.0V, VM = GND, VL = -7.5V) Min. 200 200 30 200 200 30 Typ. 350 350 60 350 350 60 Max. 500 500 90 500 500 90 1.0 1.0 1.0 1.0 Unit ns ns ns ns ns ns V V V V
Notes) 1. The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge. 2. For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1F or more) between each power supply pin (VH, VL) and GND. 3. To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor. -8-
CXD3412GA
Switching Waveforms
TTMH 90% TTHM VH 90%
V1A (V1B, V3A, V3B)
TTLM
10% 90%
10% 90%
TTML
VM
10%
10%
VL
TTLM 90% V2 (V4) 10% 90%
TTML
VM
10%
VL
TTLH 90% 90%
TTHL
VH
SUB
10%
10% VL
Waveform Noise
VM VCMH VCML
VCLH VCLL VL
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Measurement Circuit
Serial interface data CKI
VD HD +3.3V +15.0V -7.5V N3 L2 K2 K9 K8 K7 K1 L1 K3 J9 J8 J7 J3 J2 J1 H9 H8 H7 H3 H2 L3 G9 G8 G7
CLPDM CLPOB XSHP XSHD OSCO MCKO PBLK OSCI SSI1 VDD2 VDD5 VDD3 VDD4 VSS6 VSS2 VSS3 VSS5 CKO VSS4 XRS CKI H2 RG H1
C6
C4
C5 C5
C6
C6
M4 V2 M5 VH M6 VL E1 D9 L8 L9 R1 C2 R1 C1 C2 C1 C2 C2 C2 C1 C2 C2 C1 C2 R1 C2 R2 C1 C2 C2 C1 C2 C2 R1 SSGSL VDD1
CLPDMI G3 CLPOBI G2 ADCLK XSHPI XSHDI PBLKI DVDD2 DVSS3 H1 F9 F8 F7 F3 F2
M1 SCK1 M2 VD M3 TEST1 N4 V4 N5 V1B N6 V3B M7 TEST2 M8 RST R1 M9 WEN N1 SEN1 N2 HD L4 L5 L6 VM V1A V3A CXD3412GA
ADCLKI G1 AVDD1 AVSS1 AVSS2 DVSS2 DVSS1 DVDD1 AVDD2 C2 C1 D6 D7 D8 CCDIN C4 C3
TEST3 TEST5 TEST4 AVDD5 AVDD4 AVDD3 AVSS4 AVSS6 AVSS3 AVSS5 SCK2 SEN2 SSI2 NC NC C8 D2 D1 D0 C7 D5 D4 D3 C9
E9 D9 E7 F1 E3 E2 E8 D8 D7 D3 D2 D1 C9 C8 C7
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C2 C2
R1
N7 SUB C3 L7 VSS1
N8 SNCSL N9 ID/EXP
A2 A1 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B9 B8 C1 C2 C3 C4 C5 C6
CXD3412GA
C1: 3300pF R1: 30
C2: 560pF R2: 10
C3: 820pF
C4: 8pF
C5: 215pF
C6: 10pF
CXD3412GA
AC Characteristics AC characteristics between the serial interface clocks
0.8VDDd SSI1 SCK1 SEN1 SEN1 ts2 0.2VDDd 0.8VDDd 0.2VDDd ts1 0.2VDDd ts3 0.8VDDd
th1
(Within the recommended operating conditions) Symbol ts1 th1 ts2 ts3 Definition SSI1 setup time, activated by the rising edge of SCK1 SSI1 hold time, activated by the rising edge of SCK1 SCK1 setup time, activated by the rising edge of SEN1 SEN1 setup time, activated by the rising edge of SCK1 Min. 20 20 20 20 Typ. Max. Unit ns ns ns ns
Serial interface clock internal loading characteristics (1)
Example: During frame mode VD HD
V1A Enlarged view HD
0.2VDDd
V1A ts1 SEN1 0.8VDDd 0.2VDDd th1
Be sure to maintain a constantly high SEN1 logic level near the falling edge of the HD in the horizontal period during which V1A/B and V3A/B values take the ternary value and during that horizontal period. (Within the recommended operating conditions) Symbol ts1 th1 Definition SEN1 setup time, activated by the falling edge of HD SEN1 hold time, activated by the falling edge of HD - 11 - Min. 0 113 Typ. Max. Unit ns s
CXD3412GA
Serial interface clock internal loading characteristics (2)
Example: During frame mode VD HD Enlarged view
VD HD
0.2VDDd
ts1 SEN1 0.8VDDd
th1 0.2VDDd
Be sure to maintain a constantly high SEN1 logic level near the falling edge of VD. (Within the recommended operating conditions) Symbol ts1 th1 Definition SEN1 setup time, activated by the falling edge of VD SEN1 hold time, activated by the falling edge of VD Min. 0 200 Typ. Max. Unit ns ns
Serial interface clock output variation characteristics Normally, the serial interface data is loaded to the CXD3412GA at the timing shown in "Serial interface clock internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is loaded to the CXD3412GA and controlled at the rising edge of SEN1. See "Description of Operation".
SEN1
0.8VDDd
Output signal tpdPULSE
(Within the recommended operating conditions) Symbol Definition Min. 15 Typ. Max. 100 Unit ns
tpdPULSE Output signal delay, activated by the rising edge of SEN1
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CXD3412GA
RST loading characteristics
RST
0.2VDDd tw1
0.2VDDd
(Within the recommended operating conditions) Symbol tw1 RST pulse width Definition Min. 28 Typ. Max. Unit ns
VD and HD phase characteristics
VD
0.2VDDd ts1 th1 0.2VDDd
0.2VDDd
HD
(Within the recommended operating conditions) Symbol ts1 th1 Definition VD setup time, activated by the falling edge of HD VD hold time, activated by the falling edge of HD Min. 0 0 Typ. Max. Unit ns ns
HD loading characteristics
HD
0.2VDDd ts1 th1 0.8VDDd
0.2VDDd
MCKO
MCKO load capacitance = 10pF (Within the recommended operating conditions) Symbol ts1 th1 Definition HD setup time, activated by the rising edge of MCKO HD hold time, activated by the rising edge of MCKO Min. 20 0 Typ. Max. Unit ns ns
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CXD3412GA
Output variation characteristics
MCKO
0.8VDDd
WEN, ID/EXP tpd1
WEN and ID/EXP load capacitance = 10pF (Within the recommended operating conditions) Symbol tpd1 Definition Time until the above outputs change after the rise of MCKO Min. 25 Typ. Max. 70 Unit ns
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CXD3412GA
CCD Signal Processor Block Electrical Characteristics DC Characteristics Item Pins Symbol VDDe VDDf (Fc = 22.5MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25C) Conditions Min. 3.0 3.0 Typ. Max. Unit 3.3 3.3 3.6 3.6 V V
Supply voltage 1 DVDD1 Supply voltage 2 DVDD2 AVDD1, AVDD2, Supply voltage 3 AVDD3, AVDD4, AVDD5 Analog input capacitance CCDIN
VDDg
3.0
3.3
3.6
V
CIN
15 1.8
pF V
Input voltage
SCK2, SSI2, VI+ SEN2, TEST3, TEST4, XSHDI, XSHPI, ADCLKI, VI- CLPOBI, CLPDMI, PBLKI ADCLKI D0 to D9 VOH VOL Feed current where IOH = -2.0mA VDDe - 0.9 Pull-in current where IOL = 2.0mA
1.1
V
A/D clock duty Output voltage
50 0.4
% V V
Analog Characteristics Item CCDIN input voltage amplitude PGA maximum gain PGA minimum gain ADC resolution ADC maximum conversion rate ADC integral non-linearity error ADC differential non-linearity error Signal-to-noise ratio CCDIN input voltage clamp level CCD optical black signal clamp level Fc max EL ED SNR CLP OB Symbol VIN Gmax Gmin
(Fc = 22.5MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25C) Conditions PGA gain = 0dB, output full scale PGA gain setting data = "3FFh" PGA gain setting data = "000h" 22.5 PGA gain = 0dB PGA gain = 0dB CCDIN input connected to GND via a coupling capacitor PGA gain = 0dB OBLVL = "8h" PGA gain = 0dB 1.0 0.5 77 1.5 32 Min. 900 42 -6 10 Typ. Max. Unit 1100 mV dB dB bit MHz LSB LSB dB V LSB
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CXD3412GA
AC Characteristics AC characteristics between the serial interface clocks
0.8VDD SSI2 SCK2 SEN2 SEN2 ts2 0.2VDD 0.8VDD ts1 0.2VDD ts3 0.8VDD th1
The setting values are reflected to the operation 6 ADCLKI clocks after the serial data is loaded at the rise of SEN2. (Fc = 22.5MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25C) Symbol tp1 ts1 th1 ts2 ts3 SCK2 clock period SSI2 setup time, activated by the rise of SCK2 SSI2 hold time, activated by the rise of SCK2 SCK2 setup time, activated by the rise of SEN2 SEN2 setup time, activated by the rise of SCK2 Definition Min. 100 30 30 30 30 Typ. Max. Unit ns ns ns ns ns
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CXD3412GA
CDS/ADC Timing Chart
N CCDIN
N+1
N+2
N+3
XSHPI
XSHDI tw1
ADCLKI DL
D0 to D9
N - 10
N-9
N-8
N-7
Set the input pulse polarity setting data D13, D14 and D15 of the serial interface data to "0". (Fc = 22.5MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25C) Symbol tw1 DL ADCLKI clock period ADCLKI clock duty Data latency Definition Min. 44 50 9 Typ. Max. Unit ns % clocks
Preblanking Timing Chart
PBLKI 11 Clocks
ADCLKI
11 Clocks D0 to D9 All "0"
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CXD3412GA
Description of Operation Pulses output from the CXD3412GA's timing generator block are controlled mainly by the RST pin and by the serial interface data. The Pin Status Table is shown below, and the details of serial interface control are described on page 20 and thereafter. Pin Status Table Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 C1 C2 C3 C4 C5 C6 C7 C8 C9 D1 D2 D3 D7 Symbol NC NC SCK2 SSI2 TEST3 AVSS4 C8 AVSS6 AVDD5 D2 D1 D0 SEN2 TEST5 AVDD4 C7 AVDD3 AVSS3 D5 D4 D3 TEST4 AVSS5 C9 C3 C4 CCDIN D8 D7 D6 C1 CAM SLP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- STB RST Pin No. D8 D9 E1 E2 E3 E7 E8 E9 F1 F2 F3 F7 F8 F9 G1 G2 G3 G7 G8 G9 H1 H2 H3 H7 H8 H9 J1 J2 J3 J7 J8 - 18 - Symbol C2 AVSS1 D9 DVDD1 DVSS1 AVSS2 AVDD2 AVDD1 DVSS2 DVSS3 DVDD2 PBLKI XSHDI XSHPI ADCLKI CLPOBI CLPDMI PBLK XSHD XSHP ADCLK CLPOB CLPDM XRS VDD4 VDD3 CKI CKO VSS5 VSS3 H1 ACT L ACT ACT ACT ACT -- -- L ACT ACT ACT ACT ACT ACT ACT ACT L L L L L L L -- -- ACT L ACT ACT CAM SLP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- L L L L L L L H ACT ACT ACT H H ACT STB RST
CXD3412GA
Pin No. J9 K1 K2 K3 K7 K8 K9 L1 L2 L3 L4 L5 L6 L7 L8 L9 M1
Symbol H2 OSCO MCKO VDD5 VDD2 RG VSS2 OSCI SSI1 VSS4 VM V1A V3A VSS1 SSGSL VDD1 SCK1
CAM ACT ACT ACT
SLP L ACT ACT -- --
STB L ACT L
RST ACT ACT ACT
Pin No. M2 M3 M4 M5 M6
Symbol VD1 TEST1 V2 VH VL TEST2 RST WEN SEN1 HD1 VSS6 V4 V1B V3B SUB SNCSL ID/EXP
CAM ACT ACT
SLP L -- VM -- -- --
STB L VM
RST H VM
ACT ACT ACT
L -- ACT ACT -- --
L ACT ACT
ACT ACT DIS
M7 M8 M9 N1 N2 N3
ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT
ACT L ACT L -- VM VH VH VH ACT L
ACT L ACT L VM VH VH VH ACT L
L L DIS H VL VM VL VL ACT L
ACT ACT ACT ACT
VH VH -- ACT -- ACT
VH VH ACT ACT
VM VL ACT DIS
N4 N5 N6 N7 N8 N9
1 It is for output. For input, all items are "ACT". Note) ACT means that the circuit is operating, and DIS means that loading is stopped. L indicates a low output level, and H a high output level in the controlled status. Also, VH, VM and VL indicate the voltage levels applied to VH (Pin M5), VM (Pin L3) and VL (Pin M6), respectively, in the controlled status.
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CXD3412GA
Timing Generator Block Serial Interface Control The CXD3412GA's timing generator block basically loads and reflects the timing generator block serial interface data sent in the following format in the readout portion at the falling edge of HD. Here, readout portion specifies the horizontal period during which V1A/B and V3A/B, etc. take the ternary value. Note that some items reflect the timing generator block serial interface data at the falling edge of VD or the rising edge of SEN1.
SSI1 SCK1 SEN1
00
01
02
03
04
05
06
07
41
42
43
44
45
46
47
There are two categories of timing generator block serial interface data: CXD3412GA timing generator block drive control data (hereafter "control data") and electronic shutter data (hereafter "shutter data"). The details of each data are described below.
- 20 -
CXD3412GA
Control Data Data D00 to D07 Symbol CHIP Chip enable Category switching Drive mode switching Electronic shutter mode switching1 HTSG control switching1 Internal SSG function switching -- Wide CLPOB generation switching2 ID/EXP output switching CLPOB waveform pattern switching ADCLK logic phase switching Standby control -- Sunction Data = 0 Data = 1 RST All 0 All 0 All 0 0 0 0 All 0 0 0 All 0 1 0 All 0 All 0
10000001 Enabled Other values Disabled See D08 to D09 CTG. See D10 to D12 MODE. OFF OFF NTSC equivalent -- OFF ID ON ON PAL equivalent -- ON EXP
D08, CTG D09 D10 to D12 D13 D14 D15 D16 to D31 D32 D33 MODE SMD HTSG PTSG -- FGOB EXP
D34, PTOB D35 D36, LDAD D37 D38, STB D39 D40 to D47 --
See D34 to D35 PTOB. See D36 to D37 LDAD. See D38 to D39 STB. -- --
1 See D13 SMD. 2 See D32 FGOB.
- 21 -
CXD3412GA
Shutter Data Data Symbol D00 to D07 CHIP Chip enable Category switching Electronic shutter vertical period specification Electronic shutter horizontal period specification High-speed shutter position specification Function Data = 0 Data = 1 RST All 0 All 0 All 0 All 0 All 0 All 0
10000001 Enabled Other values Disabled See D08 to D09 CTG. See D10 to D19 SVD.
D08, CTG D09 D10 to D19 D20 to D31 D32 to D41 D42 to D47 SVD
SHD
See D20 to D31 SHD.
SPL
See D32 to D41 SPL.
--
--
--
- 22 -
CXD3412GA
Detailed Description of Each Data Shared data: D08 , D09 CTG [Category] Of the data provided to the CXD3412GA by the serial interface, the CXD3412GA loads D10 and subsequent data to each data register as shown in the table below according to the conbination of D08 and D09 . D09 0 0 1 D08 0 1 X Description of operation Loading to control data register Loading to shutter data register Test mode
Note that the CXD3412GA can apply these categories consecutively within the same vertical period. However, care should be taken as the data is overwritten if the same category is applied. Control data: D10 to D12 MODE [Drive mode] The CXD3412GA timing generator block drive mode can be switched as follows. However, the drive mode bits are loaded to the CXD3412GA and reflected at the falling edge of VD. D12 0 0 0 0 1 1 D11 0 0 1 1 0 1 D10 0 1 0 1 X X Description of operation Draft mode (sextuple speed: default) Frame mode (A field read out) Frame mode (B field read out) Frame mode AF1 mode AF2 mode
Control data: D15 PTSG [Internal SSG output pattern] The CXD3412GA internal SSG output pattern can be switched as follows. However, the internal SSG output pattern bits are loaded to the CXD3412GA and reflected at the falling edge of VD. D15 0 1 Description of operation NTSC equivalent pattern output PAL equivalent pattern output
VD period in each pattern is defined as follows. However, care should be taken that HD period is changing by the mode. Frame mode NTSC equivalent pattern PAL equivalent pattern 885H + 810ck 884H + 1104ck Draft mode 342H + 2592ck AF1 mode 171H + 1296ck AF2 mode 85H + 1960ck
285H + 1455ck x 2 142H + 1384ck + 1383ck 71H + 1384ck
See the Timing Charts for the actual operation.
- 23 -
CXD3412GA
Control data: D32 FGOB [Wide CLPOB generation] This controls wide CLPOB generation during the vertical OPB period. See the Timing Charts for the actual operation. The default is "OFF". D32 0 1 Description of operation Wide CLPOB generation OFF Wide CLPOB generation ON
Control data: D34 , D35 PTOB [CLPOB waveform pattern] This indicates the CLPOB waveform pattern. The default is "Normal". D35 0 0 1 1 D34 0 1 0 1 Waveform pattern (Normal) (Shifted rearward) (Shifted forward) (Wide)
Control data: D36 , D37 LDAD [ADCLK logic phase] This indicates the ADCLK logic phase adjustment data. The default is 90 relative to MCKO. D37 0 0 1 1 D36 0 1 0 1 Degree of adjustment () 0 90 180 270
Control data: D38 , D39 STB [Standby] The operating mode is switched as follows. However, the standby bits are loaded to the CXD3412GA and control is applied immediately at the rising edge of SEN1. D39 X 0 1 D38 0 1 1 Symbol CAM SLP STB Operating mode Normal operating mode Sleep mode Standby mode
See the Pin Status Table for the pin status in each mode.
- 24 -
CXD3412GA
Control data/shutter data: [Electronic shutter] The CXD3412GA realizes various electronic shutter functions by using control data D13 SMD and D14 HTSG and shutter data D10 to D19 SVD, D20 to D31 SHD and D32 to D41 SPL. These functions are described in detail below. First, the various modes are shown below. These modes are switched using control data D13 SMD. D13 0 1 Description of operation Electronic shutter stopped mode Electronic shutter mode
The electronic shutter data is expressed as shown in the table below using D20 to D31 SHD as an example. However, MSB (D31) is a reserve bit for the future specification, and it is handled as a dummy on this IC. MSB D31 X D30 D29 D28 D27 0 1 0 1 1 D26 D25 D24 D23 1 C 0 0 0 0 1 LSB D22 D21 D20 3 1 SHD is expressed as 1C3h .
[Electronic shutter stopped mode] During this mode, all shutter data items are invalid. SUB is not output in this mode, so the shutter speed is the accumulation time for one field. [Electronic shutter mode] During this mode, the shutter data items have the following meanings. Symbol SVD SHD SPL Data D10 to D19 D20 to D31 D32 to D41 Description Number of vertical periods specification (000h SVD 3FFh) Number of horizontal periods specification (000h SHD 7FFh) Vertical period specification for high-speed shutter operation (000h SPL 3FFh)
Note) The bit data definition area is assured in terms of the CXD3412GA functions, and does not assure the CCD characteristics. The period during which SVD and SHD are specified together is the shutter speed. An image of the exposure time calculation formula is shown below. In actual operation, the precise exposure time is calculated from the operating frequency, VD and HD periods, decoding value during the horizontal period, and other factors. (Exposure time) = SVD + {(number of HD per 1V) - (SHD + 1)} Concretely, when specifying high-speed shutter, SVD is set to "000h". (See the figure.) During low-speed shutter, or in other words when SVD is set to "001h" or higher, the serial interface data is not loaded until this period is finished. The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of horizontal periods applied to SHD can be considered as (number of SUB pulses - 1).
- 25 -
CXD3412GA
VD
SHD
SVD
V1A SUB WEN EXP SMD SVD SHD 1 002h 10Fh 1 000h 050h
Exposure time
Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the low-speed shutter period. In the case below, SUB is output based on SHD at the SPL vertical period out of (SVD + 1) vertical periods.
SPL 000 VD SHD V1A SUB WEN EXP SMD SPL SVD SHD 1 001h 002h 10Fh 1 000h 000h 0A3h 001 SVD 002
Exposure time
Incidentally, SPL is counted as "000h", "001h", "002h" and so on in conformance with SVD. At this time, performing SPL > SVD setting applies to the state of SPL = SVD correspondingly. Using this function it is possible to achieve smooth exposure time transitions when changing from low-speed shutter to high-speed shutter or vice-versa. - 26 -
CXD3412GA
[HTSG control mode] This mode controls the V1A/B and V3A/B ternary level outputs (readout pulse block) using D14 HTSG. When control starts, V pulse modulation during readout period is not generated and the normal V transfer is performed. D14 0 1 Description of operation Readout pulse (SG) normal operation HTSG control mode
VD
V1A SUB VCK WEN EXP HTSG SMD 0 1 1 0 0 1
Exposure time
[EXP pulse] The ID/EXP (Pin 9) output can be switched between the ID pulse or the EXP pulse using D33 EXP. The default is the "ID" pulse. See the Timing Charts for the ID pulse. The EXP pulse indicates the exposure time when it is high. In the draft mode, the transition point is the last SUB pulse falling edge, and midpoint value (1443ck) of each V1A/B and V3A/B ternary output falling edge. When there is no SUB pulse, the later ternary output falling edge (1538ck) is used. In the frame mode, the transition point is the last SUB pulse falling edge, and each V1A/B and V3A/B ternary output falling edge (1348ck). When there is no SUB pulse, the V pulse modulation falling edge just after ternary output (1386ck) is used. In addition, switching from ID to EXP is performed at the timing (ID transition point of the horizontal period where V1A/B and V3A/B ternary output) and reset to low. See the EXP pulse indicated in the explanatory diagrams under Electronic Shutter for an image of operation.
- 27 -
Chart-1
Vertical Direction Timing Chart
MODE Frame mode
A Field
Applicable CCD image sensor * ICX412
B Field
VD
877 886 1 96 101 877 886 1 95 101
HD SUB C V1A
High-speed sweep block
A
C
High-speed sweep block
B
V1B V2
V3A
1542
1544
1546
1548
1550
1543
1545
1547
1549
- 28 -
V3B V4 CCD OUT PBLK CLPOB Wide CLPOB CLPDM ID/EXP WEN
1 3 5 7 1 3 5 7 9 11 2 4 6 8 2 4 6 8 10
CXD3412GA
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. 1560 stages are fixed for high-speed sweep block. VD of this chart is NTSC equivalent pattern (885H + 810ck units). For PAL equivalent pattern, it is 884H + 1104ck units.
Chart-2
Vertical Direction Timing Chart
MODE Draft mode
Applicable CCD image sensor * ICX412
VD
260 287 1 2 260 287 1 2
HD SUB D V1A V1B V2 D
V3A V3B V4
1525 1527 1532 1534 1537 1539 1544 1546 1525 1527 1532 1534 1537 1539 1544 1546
1549
PBLK CLPOB Wide CLPOB CLPDM ID/EXP WEN
1549
- 29 -
CCD OUT
6 3 10 15 22 27 30 4 1 8 13 20 25 28
6 3 10 15 22 27 30 4 1 8 13 20 25 28
CXD3412GA
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. VD of this chart is NTSC equivalent pattern (285H + 1455ck + 1455ck units). For PAL equivalent pattern, it is 342H + 2592ck units.
Chart-3
Vertical Direction Timing Chart
MODE AF1 mode
Applicable CCD image sensor * ICX412
VD
131 144 2 14 131 144 2 14
HD SUB E V1A
High-speed sweep block
D
E
Frame shift block
E
High-speed sweep block
D
E
Frame shift block
V1B V2
V3A
V3B V4
1112 1114 1117 1119 1112 1114 1117 1119 421 423 428 430 433 435 440 442 421 423 428 430 433 435
CCD OUT PBLK CLPOB Wide CLPOB CLPDM ID/EXP WEN
6 4
6 4
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. 75 stages are fixed for high-speed sweep block; 68 stages are fixed for frame shift block. VD of this chart is NTSC equivalent pattern (142H + 1384ck + 1383ck units). For PAL equivalent pattern, it is 171H + 1296ck units. High-speed sweep block starts from 159H.
440 442
- 30 -
CXD3412GA
Chart-4
Vertical Direction Timing Chart
MODE AF2 mode
Applicable CCD image sensor * ICX412
VD
54 72 2 21 54 72 2 21
HD SUB E V1A
High-speed sweep block
D
E
Frame shift block
E
High-speed sweep block
D
E
Frame shift block
V1B V2
V3A
V3B V4
862 867 673 675 680 682 685 687 692 694 860 862 865 867 673 675 680 682 685 687
860
PBLK CLPOB Wide CLPOB CLPDM ID/EXP WEN
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. 116 stages are fixed for high-speed sweep block; 110 stages are fixed for frame shift block. VD of this chart is NTSC equivalent pattern (71H + 1384ck units). For PAL equivalent pattern, it is 85H + 1960ck units. High-speed sweep block starts from 68H. However, in this case, NTSC equivalent pattern frame rate is 0.5ck longer than 1/120s.
865
CCD OUT
6 4
6 4
692 694
- 31 -
CXD3412GA
Chart-5
Horizontal Direction Timing Chart
MODE Frame mode
Applicable CCD image sensor * ICX412
(2544) 0
50
100
150
200
250
300
350
400
450
500
550
HD MCKO
4 52 428 456/460/464
H1 H2
162 276 238 352 314 200 390
V1A/B V2
124
V3A/B V4
52 120 454
SUB
52
- 32 -
PBLK
16 42 34 24 50 50 50 458 430 454
CLPOB (1)
8
CLPOB (2) CLPOB (3)
8
CLPOB (4) CLPOB (wide) CLPDM
124
ID/EXP
124
WEN
The HD of this chart indicates the actual CXD3412GA load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.3 to 19.0s (when the drive frequency is 22.5MHz). This chart shows a period of 124ck (5.5s). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. ID/EXP of this chart shows ID. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-1. CLPOB (wide) is output at the timing shown above at the position shown in Chart-1.
CXD3412GA
Chart-6
Horizontal Direction Timing Chart
MODE Draft mode, AF1 mode, AF2 mode
Applicable CCD image sensor * ICX412
(2624) 0
50
100
150
200
250
300
350
400
450
500
550
HD MCKO
4 52 508 536/540/544
H1 H2
140 188 172 220 204 156 236 252 284 268 300 332 364 316 348 380 412 396 428 460 492 444 476
V1A/B V2
124
V3A/B V4
52 120 534
SUB
- 33 -
52
PBLK
16 42 34 24 50 50 50 538 510 534
CLPOB (1)
8
CLPOB (2) CLPOB (3)
8
CLPOB (4) CLPOB (wide) CLPDM
124
ID/EXP
124
WEN
The HD of this chart indicates the actual CXD3412GA load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.3 to 19.0s (when the drive frequency is 22.5MHz). This chart shows a period of 124ck (5.5s). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. ID/EXP of this chart shows ID. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-2, 3 and 4. CLPOB (wide) is output at the timing shown above at the position shown in Chart-2, 3 and 4.
CXD3412GA
Chart-7
Horizontal Direction Timing Chart (High-speed sweep: C)
MODE Frame mode
Applicable CCD image sensor * ICX412
(2544) 0
50
100
150
200
250
300
350
400
450
500
550
HD MCKO
4 52 428 456/460/464
H1 H2
52 128 90 166 128 90 166 204 242 204 242 280 318 280 318 356 394 356 394 432 470 432 470 508 546 508 546
V1A/B V2
52
V3A/B
- 34 -
V4 #1
52 120
#2
#3
#4
SUB PBLK CLPOB CLPDM ID/EXP WEN
The HD of this chart indicates the actual CXD3412GA load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.3 to 19.0s (when the drive frequency is 22.5MHz). This chart shows a period of 124ck (5.5s). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. ID/EXP of this chart shows ID. High-speed sweep of V1A/B, V2, V3A/B and V4 is performed up to 93H 580ck (#1560).
CXD3412GA
Chart-8
Horizontal Direction Timing Chart (Frame shift, High-speed sweep: E)
MODE AF1 mode, AF2 mode
Applicable CCD image sensor * ICX412
(2624) 0
50
100
150
200
250
300
350
400
450
500
550
HD MCKO
4 52 508 536/540/544
H1 H2
68 116 100 148 132 84 164 180 242 196 228 260 292 244 276 308 340 324 356 388 420 372 404 436 468 452 484 516 548 500 532
V1A/B V2
52
V3A/B V4 #1
52 120
- 35 -
#2
SUB
52
PBLK
16 42
CLPOB CLPDM ID/EXP
124
WEN
The HD of this chart indicates the actual CXD3412GA load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.3 to 19.0s (when the drive frequency is 22.5MHz). This chart shows a period of 124ck (5.5s). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. ID/EXP of this chart shows ID. PBLK, CLPOB, ID/EXP and WEN are output at the timing shown above at the position shown in Chart-3 and 4. Frame shift of V1A/B, V2, V3A/B and V4 is performed up to 11H 2548ck (#68) in AF1 mode and 18H 308ck (#110) in AF2 mode. In addition, high-speed sweep is performed up to 141H 2612ck (#75) in AF1 mode and 70H 2612ck (#116) in AF2 mode.
CXD3412GA
Chart-9
Horizontal Direction Timing Chart
MODE Frame mode
Applicable CCD image sensor * ICX412
1196
1234
1272
1310
1348
(2544) 0
1386
(2544) 0
124
162
200
238
276
314
352
HD [A Field] V1A [A]
V1B V2 V3A V3B
V4 [B Field] V1A V1B V2 V3A [B]
V3B V4
390
- 36 -
CXD3412GA
The HD of this chart indicates the actual CXD3412GA load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.3 to 19.0s (when the drive frequency is 22.5MHz). This chart shows a period of 124ck (5.5s). Internal SSG is at this timing.
Chart-10 Horizontal Direction Timing Chart
MODE Draft mode, AF1 mode, AF2 mode
Applicable CCD image sensor * ICX412
1158
1196
1234
1272
1310
1348
1386
1424
1462
1500
1538
(2624) 0
1576 1592 1608 1624 1640 1656 1672 1688
(2544) 0
HD [D] V1A
V1B V2
V3A V3B V4
The HD of this chart indicates the actual CXD3412GA load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.3 to 19.0s (when the drive frequency is 22.5MHz). This chart shows a period of 124ck (5.5s). Internal SSG is at this timing.
124 140 156 172 188 204 220 236 252 268 284 300 316 332 348 364 380 396 412 428 444 460 476 492
- 37 -
CXD3412GA
Chart-11 High-Speed Phase Timing Chart
MODE
Applicable CCD image sensor * ICX412
HD HD' CKI CKO ADCLK
1 52 428/508
MCKO H1
- 38 -
H2 RG XSHP XSHD XRS
HD' indicates the HD which is the actual CXD3412GA load timing. The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse. The logical phase of ADCLK can be specified by the serial interface data.
CXD3412GA
Chart-12 Vertical Direction Sequence Chart
MODE Draft Frame Draft
Applicable CCD image sensor * ICX412
VD
V1A
V1B V2
V3A
V3B
- 39 -
V4 SUB Mechanical shutter Exposure time CCD OUT MODE SMD SHD 0 1 050h A A 0 1 050h B B 0 1 050h C C 0 1 050h 0 1 050h D E E 3 0 000h E 3 0 000h 0 1 050h Close Open F F 0 1 050h
This chart is a drive timing chart example of electronic shutter normal operation. Data exposed at D includes a blooming component. For details, see the CCD image sensor data sheet. The CXD3412GA does not generate the pulse to control mechanical shutter operation. The switching timing of drive mode and electronic shutter data is not the same.
CXD3412GA
CXD3412GA
CCD Signal Processor Block Serial Interface Control The CXD3412GA's CCD signal processor block basically loads the CCD signal processor block serial interface data sent in the following format at the rising edge of SEN2, and the setting values are then reflected to the operation 6 ADCLKI clocks after that. CCD signal processor block serial interface control requires clock input to ADCLKI in order to load and reflect the serial interface data to operation, so this should normally be performed when the timing generator block is in the normal operation mode.
SSI2 SCK2 SEN2 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15
There are four categories of CCD signal processor block serial interface data: standby control data, PGA gain setting data, OB clamp level setting data, and input pulse polarity setting data. Note that when data from multiple categories is loaded consecutively, the data for the category loaded last is valid and data from other categories is lost. When transferring data from multiple categories, raise SEN2 for each category and wait until the setting value 6 ADCKLI clocks after that has been reflected to operation, then transmit the next category. The detail of each data are described below. Standby Control Data Data D00 D01 to D03 D04 to D14 D15 Symbol TEST CTG Test code Category switching Function Data = 0 Set to 0. D01 to D03 CTG Data = 1
FIXED STB
-- Standby control
Set to All 0. Normal operation mode Standby mode
PGA Gain Setting Data Data D00 D01 to D03 Symbol TEST CTG Test code Category switching -- PGA gain setting data - 40 - Function Data = 0 Set to 0. D01 to D03 CTG Set to All 0. See D06 to D15 GAIN. Data = 1
D04, FIXED D05 D06 to D15 GAIN
CXD3412GA
OB Clamp Level Setting Data Data D00 D01 to D03 D04 to D11 D12 to D15 Symbol TEST CTG Test code Category switching -- Function Data = 0 Set to 0. D01 to D03 CTG Data = 1
FIXED
Set to All 0.
OBLVL
OB clamp level setting data
See D12 to D15 OBLVL.
Input Pulse Polarity Setting Data Data D00 D01 to D03 D04 to D12 D13 to D15 Symbol TEST CTG Test code Category switching -- Function Data = 0 Set to 0. D01 to D03 CTG Data = 1
FIXED
Set to All 0.
POL
Input pulse polarity setting data
Set to All 0.
- 41 -
CXD3412GA
Detailed Description of Each Data Shared data: D01 to D03 CTG [Category] Of the data provided to the CXD3412GA by the CCD signal processor block serial interface, the CXD3412GA loads D04 and subsequent data to each data register as shown in the table below according to the combination of D01 to D03 . D01 0 0 0 0 1 D02 0 0 1 1 X D03 0 1 0 1 X Description of operation Loading to standby control data register Loading to PGA gain setting data register Loading to OB clamp level setting data register Loading to input pulse polarity setting data register Access prohibited
Standby control data: D15 STB [Standby] The operating mode of the CCD signal processor block is switched as follows. When the CCD signal processor block is in standby mode, only the serial interface is valid. D00 0 1 Description of operation Normal operating mode Standby mode
PGA gain setting data: D06 to D15 GAIN [PGA gain] The CXD3412GA can set the programmable gain amplifier (PGA) gain from -6dB to +42dB in 1024 steps by using PGA gain setting data D06 to D15 GAIN. The PGA gain setting data is expressed as shown in the table below using D06 to D15 GAIN. MSB D06 D07 D08 D09 0 1 1 1 1 C D10 D11 D12 D13 0 0 0 0 3 D14 1 LSB D15 1 GAIN is expressed as 1C3h .
For example, when GAIN is set to "000h", "080h", "220h", "348h" and "3FFh", the respective PGA gain setting values are -6dB, 0dB, +20dB, +34dB and +42dB.
- 42 -
CXD3412GA
OB clamp level setting data: D12 to D15 OBLVL [OB clamp output] The CXD3412GA can set the OPB clamp output value from 0 to 60LSB in 4LSB steps by using CCD signal processor block control data D12 to D15 OBLVL. The OPB clamp output setting data is expressed as shown in the table below using D12 to D15 OBLVL. MSB D12 D13 D14 0 1 6 1 LSB D15 0 OBLVL is expressed as 6h .
For example, when OBLVL is set to "0h", "1h", "8h" and "Fh", the respective OPB clamp output setting values are 0LSB, 4LSB, 32LSB and 60LSB.
- 43 -
Application Circuit Block Diagram
C7 0.1F C8 0.1F
B7 A7
F9 F8 F7 G3 G2 CCD ICX412 CCDOUT 1F 1F 390pF 390pF 240pF CCDIN C1 C2 C3 C4 C9
G9 G8 G7 H3 H2 H1
G1
C9 0.1F
C6 A2 NC NC D0 (LSB) D1 D2 D3 D4 D5 D6 D7 D8 D9 (MSB) CKO MCKO VD HD ID/EXP WEN RST SNCSL SSGSL Signal Processor Block
CLPDMI
CLPOBI
ADCLKI
CLPDM
CLPOB
ADCLK
XSHDI
XSHPI
PBLKI
XSHD
XSHP
PBLK
D7 D8 C7 C8
A1 B3 B2 B1 C3 C2 C1 D3 D2
H1 H2 RG V1A V1B V2 V3A V3B V4 SUB
D1 J8 J9 K8 L5 N5 M4 L5 N6 N4 N7 N9 M9 M8 N8 L8 J1 K1 L1 M3 M7 A5 C4 B5 L2 N1 M1 A4 B4 A3 TG/CDS/PGA/ADC CXD3412GA E1 J2 K2 M2 N2
SEN1
SCK1
SSI2
SEN2
This block diagram illustrates connections with each circuit block, and is not an actual circuit diagram. See the CCD image sensor data sheet for an example of specific circuit connections with the CCD image sensor.
TEST1
TEST2
TEST3
TEST4
TEST5
CKI
OSCO
OSCI
SCK2
SSI1
- 44 -
CXD3412GA
Controller
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
CXD3412GA
Notes on Operation 1. Be sure to start up the timing generator block VL and VH pin power supplies at the timing shown in the figure below in order to prevent the SUB pin of the CCD image sensor from going to negative potential. In addition, start up the timing generator block VDD1, VDD2, VDD3, VDD4 and VDD5 pin and CCD signal processor block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pin power supplies at the same time either before or at the same time as the VH pin power supply is started up.
15.0V
t1
20% 0V 20%
t2 t2 t1 -7.5V
2. Reset the timing generator block and CCD signal processor block during power-on. The timing generator block is reset by inputting the reset signal to the RST pin. The CCD signal processor block is reset by initializing the serial data. 3. Separate the timing generator block VDD1, VDD2, VDD3, VDD4 and VDD5 pins from the CCD signal processor block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4, and AVDD5 pins. Also, the ADC output driver stage is connected to the dedicated power supply pin DVDD1. Separating this pin from other power supplies is recommended to avoid affecting the internal analog circuits. 4. The difference in potential between the timing generator block VDD4 pin supply voltage 3 VDDc and the CCD signal processor block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pin supply voltages 1 VDDe, 2 VDDf and 3 VDDg should be 0.1V or less. 5. The timing generator block and CCD signal processor block ground pins should use a shared ground which is connected outside the IC. When the set ground is divided into digital and analog blocks, connect the timing generator block ground pins to the digital ground and the CCD signal processor block ground pins to the analog ground. The difference in potential between the timing generator block VSS1, VSS2, VSS3, VSS4, VSS5, VSS6 and VM and the CCD signal processor block DVSS1, DVSS2, DVSS3, AVSS1, AVSS2, AVSS3, AVSS4, AVSS5 and AVSS6 should be 0.1V or less. 6. Do not perform serial communication with the CCD signal processor block during the effective image period, as this may cause the picture quality to deteriorate. In addition, using SCK2, SSI2 and SEN2, which are used by the CCD signal processor block, use of the dedicated ports is recommended. When using these pins as shared ports with the timing generator block or other ICs, be sure to thoroughly confirm the effects on picture quality before use. - 45 -
CXD3412GA
Package Outline
Unit: mm
0.2
SA 8.0
96PIN LFLGA
X
12.0
0.10MAX
SB
x4
DETAIL X
(0.3)
(0.3) 0.5 A N M L K J H G F E D C B A 0.5 (0.3) 12 3 4 5 6 7 8 9 0.8 0.5
LFLGA-96P-02 P-LFLGA96-12X8-0.8
0.8
96 -0.45 0.05 0.08 M S A B
0.9
B
0.9
(0.3) 0.5
1.2
0.8
3 - 0.50
PACKAGE STRUCTURE
PACKAGE MATERIAL ORGANIC SUBSTRATE
SONY CODE EIAJ CODE JEDEC CODE
TERMINAL TREATMENT NICKEL & GOLD PLATING TERMINAL MATERIAL PACKAGE MASS COPPER 0.3g
S
0.15
0.2
0.2
S
0.10 S
Sony Corporation
PIN 1 INDEX
1.3 MAX
- 46 -

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